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integrated circuit true rms - to - dc converter data sheet ad536a rev. e information furnished by analog devices is believ ed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no lic ense is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781 .329.4700 www.analog.com fax: 781.461.3113 ? 1976 C 2012 analog devices, inc. all rights reserved. features true rms - to - dc conversion laser trimmed to high accuracy 0.2% maximum error (ad536ak) 0.5% maximum error (ad536aj) wide response capability computes rms of ac and dc signals 450 khz bandwidth: v rms > 100 mv 2 mhz bandwidth: v rms > 1 v signal c rest factor of 7 for 1% error db output with 60 db range low power: 1.2 ma quiescent current single - or dual - supply operation monolithic integrated circuit ?55c to +125c operation (ad536as) general description the ad536a is a complete monolithic integrated circuit that performs true rms - to - dc conversion. it offers performance comparable or superior to that of hybrid or modular units costing much more. the ad536a directly computes the true rms value of any complex input waveform containing ac and dc components. a crest factor compensation scheme allows measurements with 1% error at crest factors up to 7. the wide bandwidth of the device extends the measureme n t capa bility to 300 khz with less than 3 db errors for signal levels greater than 100 m v. an important feature of the ad536a, not previously available in rms converters, is an auxiliary db output pin. the logarithm of the rms output signal is brought out to a separate pin to allow the db conversion, with a useful dynamic range of 60 db. using an externally supplied reference current, the 0 db level can be conveniently set to correspond to any input level from 0.1 v to 2 v rms. the ad536a is laser trimmed t o minimize input and output offset voltage, to optimize positive and negative waveform symmetry (dc reversal error), and to provide full - scale accuracy at 7 v rms. as a result, no external trims are required to achieve the rated unit accuracy. the input an d output pins are fully protected. the input circuitry can take overload voltages well beyond the supply levels. loss of supply voltage with the input connected to external circuitry does not cause the device to fail. the output is short - circuit protected. functional block dia gram db buffer in v in 25k? 80k? 25k? c av +v s ?v s com ad536a r l i out buffer out current mirror squarer/ divider absolute value 00504-001 + buf figure 1. the ad536a is available in two accuracy grades (j and k) for commercial temperature range (0c to 70c) applications, and one grade (s) rated for the ?55c to +125c extended range. the ad536ak offers a maximum total error of 2 mv 0.2% of reading , while the ad536aj and ad536as have maximum errors of 5 mv 0.5% of reading. all three versions are available in a hermetically sealed 14 - lead dip or a 10 - pin to - 100 metal header package . the ad536as is also available in a 20 - terminal leadless hermetically sealed ceramic chip carrier. the ad536a computes the true root - mean - square level of a complex ac (or ac plus dc) input signal and provides an equiva - lent dc output level. the true rms value of a waveform is a more useful quantity than the average rectified value because it relates directly to the power of the signal. the rms value of a statistical signal also relates to its standard deviation. an external capacitor is required to perform measurements to the fully specified accuracy. th e value of this capacitor deter mines the low frequency ac accuracy, ripple amplitude, and settling time. the ad536a operates equally well from split supplies or a single supp ly with total supply levels from 5 v to 36 v. with 1 ma quiescent supply current, the device is well suited for a wide variety of remote controllers and battery - powered instruments.
important links for the ad536a * last content update 09/07/2013 04:37 pm parametric selection tables find similar products by operating parameters documentation ad536a military data sheet an-653: improving temperature, stability, and linearity of high dynamic range rms rf power detectors an-214: ground rules for high speed circuits an-268: rms-to-dc converters ease measurement tasks rms-to-dc application guide second edition * section i: rms-dc conversion - theory * section ii: rms-dc conversion - basic design considerations * section iii: rms application circuits * appendix a: testing the critical parameters of rms converters * appendix b: input buffer amplifier requirements * appendix c: computer programs for determining computational errors, output ripple, and 1% settling time of rms converter * appendix d: new products appendix to the rms-to-dc conversion application guide (october 2002) * download the entire guide in .zip format introduction to analog rms-to-dc technology: converters and applications audio version introduction to analog rms-to-dc technology: converters and applications non-audio version adi warns against misuse of cots integrated circuits space qualified parts list design tools, models, drivers & software ad536a spice macro model evaluation kits & symbols & footprints symbols and footprints design collaboration community collaborate online with the adi support team and other designers about select adi products. follow us on twitter: www.twitter.com/adi_news like us on facebook: www.facebook.com/analogdevicesinc design support submit your support request here: linear and data converters embedded processing and dsp telephone our customer interaction centers toll free: americas: 1-800-262-5643 europe: 00800-266-822-82 china: 4006-100-006 india: 1800-419-0108 russia: 8-800-555-45-90 quality and reliability lead(pb)-free data sample & buy ad536a view price & packaging request evaluation board request samples check inventory & purchase find local distributors * this page was dynamically generated by analog devices, inc. and inserted into this data sheet. note: dynamic changes to the content on this page (labeled 'important links') does not constitute a change to the revision number of the product data sheet. this content may be frequently modified. powered by tcpdf (www.tcpdf.org)
ad536a data sheet rev. e | page 2 o f 16 table of contents features .............................................................................................. 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 5 esd caution .................................................................................. 5 pin configurations and function descriptions ........................... 6 theory of operation ........................................................................ 8 connections for db operation ................................................... 8 frequency response .....................................................................9 ac measurement accuracy and crest factor ...........................9 applications information .............................................................. 11 typical connections .................................................................. 11 optional external trims for high accuracy ......................... 11 single - supply operation ........................................................... 12 choosing the averaging time constant ................................. 12 outline dimensions ....................................................................... 14 ordering guide .......................................................................... 15 revision history 7/12 rev. d to rev. e reorganized layout ............................................................ universal changes to figure 1 .......................................................................... 1 chang es to figure 6 .......................................................................... 8 changes to figure 7 .......................................................................... 9 changes to figure 13, figure 14, and figure 15 ......................... 11 changes to figure 16, figure 17, and single - supply operation section .............................................................................................. 12 changes to figure 21 ...................................................................... 13 u pdated outline dimensions ....................................................... 14 8 /08 rev. c to rev. d changes to feature s section ............................................................ 1 changes to general description section ...................................... 1 changes to figure 1 .......................................................................... 1 changes to table 2 ............................................................................ 5 change to figure 2 ........................................................................... 5 changes to figure 15 ...................................................................... 10 changes to connections for d b operation section ................... 11 changes to figure 17 ...................................................................... 12 changes to frequency response section .................................... 12 upda ted outline dimensions ....................................................... 14 changes to ordering guide .......................................................... 15 3/06 rev. b to rev. c updated format .................................................................. universal changed product description to general description ................ 1 changes to general description ..................................................... 1 changes to table 1 ............................................................................. 3 changes to table 2 ............................................................................. 5 added pin configurat ions and function descriptions ............... 6 changed standard connection to typical connections ............. 8 changed single supply connection to single supply operation ............................................................................................ 9 changes to connections for db operation ................................. 11 changes to figure 17 ...................................................................... 12 updated outline dimensions ....................................................... 14 changes to ordering guide .......................................................... 15 6/99 rev. a to rev. b 1/76 revision 0: initial version
data sheet ad536a rev. e | page 3 of 16 specifications t a = +25c and 15 v dc, unless otherwise noted. table 1 . ad536aj ad536ak ad536as parameter min typ max min typ max min typ max unit t ransfer function v out = avg (v in ) 2 v out = a vg(v in ) 2 v out = avg (v in ) 2 conversion accuracy total error, internal trim 1 ( see figure 13) 5 0.5 2 0.2 5 0.5 mv % of rdg vs. temperatur e t min to +70c 0.1 0.01 0.05 0.005 0.1 0.005 mv % of rdg/c +70c to +125c 0.3 0.005 mv % of rdg/c vs. supply voltage 0.1 0.01 0.1 0.01 0.1 0.01 mv % of rdg/c dc reversal error 0.2 0.1 0 .2 mv % of rdg total error, external trim 1 ( see figure 16) 3 0.3 2 0.1 3 0.3 mv % of rdg error vs. crest factor 2 crest factor 1 to crest factor 2 specified accuracy specified accuracy specified accuracy crest factor = 3 ?0.1 ?0.1 ?0.1 % of rdg crest factor = 7 ?1.0 ?1.0 ?1.0 % of rdg frequency response 3 bandwidth for 1% additional error (0.09 db) v in = 10 mv 5 5 5 khz v in = 100 mv 45 45 45 khz v in = 1 v 120 120 120 khz 3 db bandwidth v in = 10 mv 90 90 90 khz v in = 100 mv 450 450 450 khz v in = 1 v 2.3 2.3 2.3 mhz averaging time constant ( see figure 19) 25 25 25 ms/f input characteristics signal range, 15 v supplies continuous rms level 0 to 7 0 to 7 0 to 7 v rms peak transient input 20 20 20 v peak continuous rms level , v s = 5 v 0 to 2 0 to 2 0 to 2 v rms peak transient input, v s = 5 v 7 7 7 v peak maximum continuous nondestructive input level (all supply voltages) 25 25 25 v peak input resistance 13.33 16.67 20 13.33 16.67 20 13.33 16.67 20 k? input offset voltage 0.8 2 0.5 1 0.8 2 mv output characteristics offset voltage, v in = com ( see figure 13) 1 2 0.5 1 2 mv vs. temperature 0.1 0.1 0.2 mv/c vs. supply vo ltage 0.1 0.1 0.2 mv/v voltage swing, 15 v supplies 0 to +11 +12.5 0 to +11 +12.5 0 to +11 +12.5 v 5 v supply 0 to +2 0 to +2 0 to +2 v db output, 0 db = 1 v rms ( see figure 7 ) error, 7 mv < v in < 7 v rms 0.4 0.6 0.2 0.3 0.5 0.6 db scale factor ?3 ?3 ?3 mv/db scale factor temperature coefficient ?0.033 ?0.033 ?0.033 db/c uncompensated +0.33 +0.33 +0.33 % of rdg/c i ref for 0 db = 1 v rms 5 20 80 5 20 80 5 20 80 a i ref range 1 100 1 100 1 100 a
ad536a data sheet rev. e | page 4 o f 16 ad536aj ad536ak ad536as parameter min typ max min typ max min typ max unit i out terminal i out scale factor 40 40 40 a/v rms i out scale factor tolerance 10 20 10 20 10 20 % output resistance 20 25 30 20 25 30 20 25 30 k? voltage compliance ?v s to (+v s ? 2.5 v) ?v s to (+v s ? 2.5 v) ?v s to (+v s ? 2.5 v) v buffer amp lifier input and output voltage range ?v s to (+v s ? 2.5v) ?v s to (+v s ? 2.5v) ?v s to (+v s ? 2.5v) v input offset voltage, r s = 25 k ? 0.5 4 0.5 4 0.5 4 mv input bias current 20 60 20 60 20 60 na input resistance 10 8 10 8 10 8 ? output current (+5 ma, (+5 ma, (+5 ma, ?130 a) ?130 a) ?130 a) short - circuit current 20 20 20 ma output resistance 0.5 0.5 0.5 ? small - signal bandwidth 1 1 1 mhz slew rate 4 5 5 5 v/s power supply voltage rated performance 15 15 15 v dual supply 3.0 18 3.0 18 3.0 18 v single supply +5 +36 +5 +36 +5 +36 v quiescent current total v s , 5 v to 36 v, t min to t max 1.2 2 1.2 2 1.2 2 ma temperature range rated performance 0 +70 0 +70 ?55 +125 c storage ?55 +150 ?55 +150 ?55 +150 c number of transistors 65 65 65 1 accuracy is specified for 0 v to 7 v rms, dc or 1 khz sine wave input with the ad536a connected as in the figure referenced . 2 error vs. crest factor is specified as an additional error for 1 v rms rectangular pulse input, pulse width = 200 s . 3 input voltages are expressed in volts rms, and error is expressed as a percent age of the reading. 4 with 2k ? external pull - down resistor.
data sheet ad536a rev. e | page 5 of 16 absolute maximum rat ings table 2 . parameter rating supply voltage dual supply 18 v single supply +36 v internal power dissipat ion 500 mw maximum input voltage 25 v peak buffer maximum input voltage v s maximum input voltage 25 v peak storage temperature range ?55c to +150c operating temperature range ad536aj/ad536ak 0c to +70c ad536as ?55c to +125c lead temperatu re (soldering , 60 sec) 300c esd rating 1000 v thermal resistance ja 1 10- pin header (h - 10 package) 150c/w 20- terminal lcc (e - 20 package) 95c/w 14- lead sb dip (d - 14 package) 95c/w 14- lead cer dip (q - 14 package) 95c/w stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied . exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution 1 ja is specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. pad numbers correspond to pin numbers for the to-100 14-lead ceramic dip package. 1 both pads shown must be connected to v in . the ad536a is available in laser-trimmed chip form. substrate connected to ?v s . +v s 14 v in 1a 1 v in 1b 1 com 10 i out 8 buf in 7 buf out 6 db 5 c av 4 ?v s 3 r l 9 0.1315 (3.340) 0.0807 (2.050) 00504-002 figure 2 . die dimensions and pad layout dimensions shown in inches and (millimeters)
ad536a data sheet rev. e | page 6 o f 16 pin configuration s and function descr iptions v in 1 nc 2 ?v s 3 c av 4 +v s 14 nc 13 nc 12 nc 11 db 5 com 10 buf out 6 r l 9 buf in 7 i out 8 nc = no connect ad536a top view (not to scale) 00504-003 figure 3. d - 14 and q - 14 packages pin configuration table 3 . d - 14 and q - 14 packages pin function descriptions pin no. mnemonic description 1 v in input voltage 2 nc no connect ion 3 ?v s negative supply voltage 4 c av averaging capacitor 5 db log (db) value of the rms output voltage 6 buf out buffer output 7 buf in buffer input 8 i out rms output current 9 r l load resistor 10 com common 11 nc no connection 12 nc no connection 1 3 nc no connection 14 +v s positive supply voltage 10 5 9 1 8 2 6 4 7 3 i out ?v s v in c av +v s db com buf out r l buf in ad536a top view (not to scale) 00504-004 figure 4. h - 10 package pin configuration table 4 . h - 10 package pin function descriptions pin no. mnemonic description 1 r l load resistor 2 com common 3 +v s positive supply voltage 4 v in input voltage 5 ?v s negative supply voltage 6 c av averaging capacitor 7 db log (db) value of the rms output voltage 8 buf out buffer output 9 buf in buffer input 10 i out rms output current
data sheet ad536a rev. e | page 7 of 16 v in nc ?v s c av +v s nc nc nc db com buf out r l buf in i out nc = no connect ad536a top view (not to scale) 20 19 1 2 3 4 5 6 7 8 13 12 11 10 9 14 15 16 17 18 nc nc nc nc nc nc 00504-005 figure 5. e - 20 package pin configuration table 5 . e - 20 package pin function description s pin no. mnemonic description 1 nc no connection 2 v in input voltage 3 nc no connection 4 ?v s negative supply voltage 5 nc no connection 6 c av averaging capacitor 7 nc no connection 8 db log (db) value of the rms output voltage 9 buf out buffer output 10 buf in buffer input 11 nc no connection 12 i out rms output current 13 r l load resistor 14 com common 15 nc no connection 16 nc no connection 17 nc no connection 18 nc no conne ction 19 nc no connection 20 +v s positive supply voltage
ad536a data sheet rev. e | page 8 o f 16 theory of operation the ad536a embodies an implicit solution of the rms equation that overcomes the dynamic range as well as other limitations inherent in a straightforward computation of rms. the actual computation performed by the ad536a follows the equation ? ? ? ? ? ? ? ? = rms v v avg rms v in 2 figure 6 is a simplified schematic of the ad536a. note that it is subdivided into four major sections: absolute value circuit (active rect ifier), squarer/divider, current mirror, and buffer amplifier. the input voltage (v in ), which can be ac or dc, is converted to a unipolar current (i 1 ) by the active rectifier s (a 1 , a 2 ). i 1 drives one input of the squarer/divider, which has the transfer fu nction i 4 = i i 2 /i 3 the output current, i 4 , of the squarer/divider drives the current mirror through a low - pass filter formed by r1 and the exter - nally connected capacitor, c av . if the r1 c av time constant is much greater than the longest period of the inpu t signal, then i 4 is effectively averaged. the current mirror returns a current i 3 , which equals avg[i 4 ], back to the squarer/divider to complete the implicit rms computation. thus, i 4 = avg [ i i 2 / i 4 ] = i i rms 14 +v s ?v s i 3 i 2 i 1 i out r l v in |v in |r ?1 absolute v alue; volt age-current converter one-quadrant squarer/divider current mirror q1 q2 q3 q4 q5 com 4 9 db out 5 buf out 6 3 8 1 buf in buffer 7 10 0.4m a fs a3 notes 1. pinouts are for 14-lead di p . 0.2m a fs r1 n? r2 n? n? n? n? r4 n? r3 n? n? 00504-106 a4 a2 a1 figure 6 . simplified schematic the current mirror also produces the output current, i out , which equals 2i 4 . i out can be used directly or can be converted to a voltage with r2 and buffered by a4 to provide a low impedance voltage output. the transfer function of the ad536a re sults in the following: v out = 2 r2 i rms = v in rms the db output is derived from the emitter of q3 because the voltage at thi s point is proportional to C log v in . the emitter follower, q5, buffers and level shifts this voltage so that the db output volta ge is zero when the externally supplied emitter current (i ref ) to q5 approximates i 3 . connections for d b operation the logarithmic (or decibel) output of the ad536a is one of its most powerful features. the internal circuit computing db works accurately o ver a 60 db range. the connections for db measurements are shown in figure 7 . select the 0 db level by adjusting r1 for the proper 0 db reference current (which is set to cancel the log output current from the squ arer/divider at the desired 0 db point). the external op amp provides a more convenient scale and allows compensation of the +0.33%/c scale factor drift of the db output pin. the temp erature - compensating resistor, r2, is available online in several style s from precision resistor company, inc., (part number at35 and part number st35). the average temperature coefficients of r2 and r3 result in the +3300 ppm required to compensate for the db output. the linear rms output is available at pin 8 on the dip or pin 10 on the header device with an output impedance of 25 k?. some applications require an additional buffer amplifier if this output is desired. for db calibration, 1. set v in = 1.00 v dc or 1.00 v rms. 2. adjust r1 for db output = 0.00 v. 3. set v in = +0.1 v dc or 0.10 v rms. 4. adjust r5 for db output = ?2.00 v. any other desired 0 db reference level can be used by setting v in and adjusting r1 accordingly. note that adjusting r5 for the proper gain automatically provides the correct temperature compensation.
data sheet ad536a rev. e | page 9 of 16 14 13 12 11 10 9 8 1 2 3 4 5 6 7 ad536a 25k? absolute value squarer/ divider current mirror 00504-107 buf v in nc ?v s c1, c av c av c2 +v s nc nc nc db com r l i out +v s 4.6v to 18v e out ?e +e 2.5v op77 ad580j r1 500k? 0db ref adjust db scale factor adjust temperature compensated db output +100mv/db ?v s +v s ?v s +v s db out 3mv/db 1 special tc compensation resistor, +3300ppm/c, precision resistor company part number at 35 or part number st35. linear rms output r6 24.9k? r3 60.4? r2 1 1k? r4 33.2k? r5 5k? buf out buf in + 0.1f 7 4 3 6 2 f igure 7 . db connection frequency response the ad536a utilizes a logarithmic circuit in performing the implicit rms computation. as with any log circuit, bandwidth is proportional to signal level. the solid lines in the graph of figure 8 represent the frequency response of the ad536a at input levels from 10 mv rms to 7 v rms. the dashed lines indicate the upper frequency limits for 1%, 10%, and 3 db of reading additional error. for example, note that a 1 v rms signal produces less than 1% of reading additional error up to 120 khz. a 10 mv signal can be measured with 1% of reading additional error (100 v) up to only 5 khz. 100 k 1 m 10 m 1 k 10 k 1 0 1 0 . 1 0 . 0 1 v out (v) 1 % 10 % 3 d b f r eq u en c y (h z) 7 v rms i n pu t 1 v rms i n pu t 100m v rms i n pu t 10m v rms i n pu t 00504-016 figure 8 . high frequency response ac measurement accur acy and crest factor crest factor is often overlooked when determining the accuracy of an ac measurement. the definition of crest factor is the ratio of the peak signal amplitude to the rms value of the signal (cf = v p /v rms). most common waveforms, such as sine and triangle waves, have relatively low crest factors (<2). waveforms that resemble low duty cycle pulse trains, such as those occurring in switching power supplies and scr circuits, have high crest factors. for example, a rectangular pulse train with a 1% duty cycle has a crest factor of 10 (cf = 1n). figure 9 illustrates a curve of reading error for the ad536a for a 1 v rms input signal with crest factors from 1 to 11. a rectan - gular pulse train (pulse width = 100 s) was used for this test because it is the worst - case waveform for rms measurement (all of the energy is contained in the peaks). the duty cycle and peak amplitude were varied to produce crest factors from 1 to 11 while maintaining a constant 1 v rms input amplitude. = duty cycle = cf = 1/? ? in (rms) = 1 v rms 100s t ? o v p 0 100s t 1 0 ?1 ?2 ?3 ?4 increase in error ( % of reading ) 1 2 3 4 5 6 7 8 9 10 11 crest factor 00504-017 figure 9. error vs. crest factor increase in error (% of reading) 1 s 10 s 100 s 1000 s pu l se w i d t h ( s ) 1 0 1 0 . 1 1 v rms c f = 3 1 v rms c f = 1 0 00504-018 figure 10 . error vs. pulse width rectangular pulse
ad536a data sheet rev. e | page 10 o f 16 6 10 16 18 vol ts (dua l supp l y) 25 20 15 10 5 0 peak input or output (v) v out v in 00504-019 figure 11 . input and output voltage ranges vs. dual supply 10 20 30 vol ts (single supp l y) 25 20 15 10 5 0 peak input or output (v) 2.5 5 v out v in 00504-022 figure 12 . input and output voltage rang es vs. single supply
data sheet ad536a rev. e | page 11 of 16 applications information typical connections the ad536a is simple to connect to for the majority of high accuracy rms measurements, requiring only an external capaci - tor to set the averaging time constant. the standard connection is shown in figure 13 through figure 15 . in this configuration, the ad536a meas ures the rms of the ac and dc level s present at the input, but shows an error for low frequency input as a function of the filter capacitor, c av , as shown in figure 19 . thus, if a 4 f capacitor is used, the additional average error at 10 hz is 0.1%; at 3 hz, the additional average error is 1%. the accuracy at higher frequencies is according to speci fication. to reject the dc input, add a capacitor in series with the input, as shown in figure 17 . note that the capacitor must be nonpolar . if the ad536a supply rails contain a considerable amount of high frequency ripple, it is advisable to bypass both supply pins to ground with 0.1 f ceramic capacitors, located as close to the device as possible. 00504-006 14 13 12 11 10 9 8 1 2 3 4 5 6 7 25k? ad536a c av v in ?v s v out +v s absolute value squarer/ divider current mirror v in nc ?v s c av +v s nc nc nc db com buf out r l buf in i out buf figure 13 . 14 - lead standard rms connection ad536a 25k? v out i out +v s c av v in ?v s absolute value squarer/ divider current mirror 00504-020 c av +v s db com buf in buf out r l buf figure 14 . 10 - pin standard rms conne ction 4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13 ad536a db +v s c av v in ?v s v out 25k? absolute value squarer/ divider current mirror 00504-021 nc ?v s c av nc nc nc com buf out r l buf in i out nc nc nc nc nc nc buf figure 15 . 20 - terminal standard rms connection the input and output signal ranges are a function of the supply voltages; these ranges are shown in figure 11 and figure 12. the ad536a can also be used in an unbuffered voltage output mode by disconnecting the input to the buffer. the output then appears unbuffered across the 25 k resistor. the buffer ampli - fier can then be used for other purposes. further, the ad536a can be used in a current output mode by disconnecting the 25 k resistor from ground. the output current is available at pin 8 ( i out , pin 10 on the h - 10 package) with a nominal scale of 40 a per v rms input positive out put . optional external tr ims for high ac curacy the accuracy and offset voltage of the ad536a is adjustable with external trims, as shown in figure 16 . r4 trims the offset. note that the offset trim circuit adds 365 in series with the internal 25 k resistor. this caus es a 1.5% increase in scale factor, which is compensated for by r1. the scale factor adjustment range is 1.5%. the trimming procedure is as follows: 1. ground the input signal, v in , and adjust r4 to provide 0 v output from pin 6. alternatively, adjust r4 to provide the correct output with the lowest expected value of v in . 2. connect the desired full - scale input level to v in , either dc or a calibrated ac signal (1 khz is the optimum frequency). 3. trim r1 to provide the correct output at pin 6. for example, 1.000 v dc input provides 1.000 v dc output. a 1.000 v peak - to - peak sine wave should provide a 0.707 v dc output. any residual errors are caused by device nonlinearity. the major advantage of external trimming is to optimize device performance for a reduced signa l range; the ad536a is internally trimmed for a 7 v rms full - scale range.
ad536a data sheet rev. e | page 12 o f 16 c av ?v s v in v out +v s 14 13 12 11 10 9 8 1 2 3 4 5 6 7 ?v s +v s ad536a 25k? 25k? absolute value squarer/ divider current mirror r4 50k? offset adjust r3 750k? r2 365? 00504-007 buf nc ?v s c av +v s nc nc nc db com buf out r l buf in i out scale f ac t or adjust r1 500? figure 16 . optional external gain and output offset trims single - supply operation refer to figure 17 for single supply - rail confi gurations between 5 v and 36 v. when powered from a single supply, the input stage (vin pin ) is internally biased at a voltage between ground and the supply, and the input signal ac coupled. biasing the device between the supply and ground is simply a matt er of connecting the com pin to an external resistor divider and bypassing to ground. the resistor values are large, minimizing power consumption, as the com pin current is only 5 a. note that the 10 k and 20 k resistors connected to the com pin ( figure 17 ) are asymmetrical, that is, the voltage at the com pin is 1/3 of the supply. this ratio of input bias to supply is optimum for the precision rectifier (aka absolute value circuit) input circuit employed for rectifying ac input waveforms a nd ensures full input symmetry for low signal voltages. capacitor c2 is required for ac input coupling, however an external dc return is unnecessary because biasing occurs internally. selectc2 for the desired low frequency breakpoint using an input resista nce of 16.7 k for the 1/rc calculation; c2 = 1 f for a cutoff at 10 hz. figure 11 and figure 12 show the input and output signal ranges for dual and single supply configurations, respectively. the load resistor, rl, provides a path to sink output sink current when an input signal is disconnected. c av v in v out +v s 14 13 12 11 10 9 8 1 2 3 4 5 6 7 ad536a 25k? absolute value squarer/ divider current mirror c2 1f nonpolarized r l 0.1f 20k? 10k? 0.1f 10k ? to 1k ? 00504-008 v in nc ?v s c av +v s nc nc nc db com buf out r l buf in i out buf figure 17 . single - supply connection choosing the averagi ng time constant the ad536a computes the rms of both ac and dc signals. if the input is a slowly varying dc signal, the output of the ad536a tracks the input exactly. at higher f requencies, the average output of the ad536a approaches the rms value of the input signal. the actual output of the ad536a differs from the ideal output by a dc (or average) error and some amount of ripple, as shown in figure 18. dc error = e o ? e o (ideal) idea l e o double frequenc y ripple a verage e o ? e o e o time 00504-009 figure 18 . typical output waveform for sinusoidal input the dc error is dependent on the input signal frequency and the value of c av . use figure 19 to determine the minimum value of c a v , which yields a given percent age of dc error above a given frequency using the standard rms connection. the ac component of the output signal is the ripple. there are two ways to reduce the ripple. the first method involves using a large value of c av . be cause the ripple is inversely proportional to c av , a tenfold increase in this capacitance affects a tenfold reduction in ripple. when measuring waveforms with high crest factors, such as low duty cycle pulse trains, the averaging time constant should be a t least 10 times the signal period. for example, a 100 hz pulse rate requires a 100 ms time constant, which corresponds to a 4 f capacitor (time constant = 25 ms per f).
data sheet ad536a rev. e | page 13 of 16 the primary disadvantage in using a large c av to remove ripple is that the settling time for a step change in input level is increased proportionately. figure 19 illustrates that the relationship between c av and 1% settling time is 115 ms for each microfarad of c av . the settling time is twice as great for decrea sing signals as it is for increasing signals. the values in figure 19 are for decreasing signals. settling time also increases for low signal levels, as shown in figure 20. 10 100 1k 10k 0.1 1 10 100 0.01 1 100k input frequency (hz) required c av (f) 0.1 1 10 100 0.01 for 1% settling time in seconds multiply reading by 0.115 0.01% error 0.1% error 10% error 1% error 1 percent dc error and percent ripple (peak) values for c av and 1% settling time for stated % of reading averaging error 1 accuracy 20% due to component tolerance 00504-010 figure 19 . error/settling time graph for use with the standard rms connection (see figure 13 through figure 15 ) 10m 100m 1 7.5 10.0 5.0 1m 10 rms input leve l (v) settling time rel a tive t o 1v rms input settling time 1.0 2.5 00504-0 1 1 figure 20 . settling time vs. input level a better method to reduce o ut put ripple is the use of a post filter. figure 21 shows a suggested circuit. if a single - pole filter is used (c3 removed, r x shorted) and c2 is approximately twice the value of c av , the ripple is reduced, as shown in figure 22 , and settling time is increased. for example, with c av = 1 f and c2 = 2.2 f, the ripple for a 60 hz input is reduced from 10% of reading to approximately 0.3% of reading. the settling time, however, is increased by approximately a factor of 3. therefore, the values of c av and c2 can be reduced to permit faster settling times while still providing substantial ripple reduction. the two - pole post filter uses an active filter stage to provide even greater ripple reduction without subs tantially increasing the settling times over a circuit with a one - pole filter. the values of c av , c2, and c3 can then be reduced to allow extremely fast settling times for a constant amount of ripple. caution should be exercised in choosing the value of c a v , beca use the dc error is dependent on this value and is independent of the post filter. for a more detailed explanation of these topics, refer to the rms to dc conversion application guide , 2n d edition , available online from analog devices, inc ., at www.analog.com . c2 v in c av +v s 14 13 12 11 10 9 8 1 2 3 4 5 6 7 ad536a 25k? absolute value squarer/ divider current mirror ?v s rx 24k? + ? + ? c3 1 v rms out 1 for single pole, short rx, remove c3. 00504-012 v in nc ?v s c av +v s nc nc nc db com buf out r l buf in i out buf figure 21 . two - pole postf ilter 1 1k 100 10k 0.1 10 10 dc error or ripple (% of reading) peak-to-peak ripple c a v = 1f dc error c av = 1f (all filters) peak-to-peak ripple c av = 1f c2 = c3 = 2.2f (two-pole) 00504-013 rx = 0? peak-to-peak ripple (one pole) c av = 1f, c2 = 2.2f frequency (hz) figure 22 . performance features of various filter types (see figure 13 to figure 15 for standard rms connection )
ad536a data sheet rev. e | page 14 o f 16 outline dimensions \ controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. 14 1 7 8 0.310 (7.87) 0.220 (5.59) pin 1 0.080 (2.03) max 0.005 (0.13) min seating plane 0.023 (0.58) 0.014 (0.36) 0.060 (1.52) 0.015 (0.38) 0.200 (5.08) max 0.200 (5.08) 0.125 (3.18) 0.070 (1.78) 0.030 (0.76) 0.100 (2.54) bsc 0.150 (3.81) min 0.765 (19.43) max 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) figure 23 . 14 - lead side - brazed ceramic dual in - line package [sbdip] (d - 14) dimensions shown in inches and (millimeters) controlling dimensions are in inches; millimeter dimensions (in p arentheses) are rounded-off inch equi v alents for reference on l y and are not appropri a te for use in design. 1 20 4 9 8 13 19 14 3 18 bot t om view 0.028 (0.71) 0.022 (0.56) 45 ty p 0.015 (0.38) min 0.055 (1.40) 0.045 (1.14) 0.050 (1.27) bsc 0.075 (1.91) ref 0.0 1 1 (0.28) 0.007 (0.18) r ty p 0.095 (2.41) 0.075 (1.90) 0.100 (2.54) ref 0.200 (5.08) ref 0.150 (3.81) bsc 0.075 (1.91) ref 0.358 (9.09) 0.342 (8.69) sq 0.358 (9.09) max sq 0.100 (2.54) 0.064 (1.63) 0.088 (2.24) 0.054 (1.37) 022106- a figure 24 . 20 - terminal ceramic lea dless chip carrier [lcc] (e - 20 - 1) dimensions shown in inches and (millimeter s) controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. 0.310 (7.87) 0.220 (5.59) 0.005 (0.13) min 0.098 (2.49) max 0.100 (2.54) bsc 15 0 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) seating plane 0.200 (5.08) max 0.785 (19.94) max 0.150 (3.81) min 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) pin 1 1 7 8 14 figure 25 . 14 - lead ceramic dual in - line package [cerdip] (q - 14) dimensions shown in inches and (millimeters)
data sheet ad536a rev. e | page 15 o f 16 controlling dimensions are in inches; millimeter dimensions (in p arentheses) are rounded-off inch equi v alents for reference on l y and are not appropri a te for use in design. dimensions per jedec s t andards mo-006-af 0.500 (12.70) min 0.185 (4.70) 0.165 (4.19) reference plane 0.050 (1.27) max 0.040 (1.02) max 0.335 (8.51) 0.305 (7.75) 0.370 (9.40) 0.335 (8.51) 0.021 (0.53) 0.016 (0.40) 1 0.034 (0.86) 0.025 (0.64) 0.045 (1.14) 0.025 (0.65) 0.160 (4.06) 0. 1 10 (2.79) 6 2 8 7 5 4 3 0. 1 15 (2.92) bsc 9 10 0.230 (5.84) bsc base & se a ting plane 36 bsc 022306- a figure 26 . 10 - pin metal header package [to - 100] (h- 10) dimensions shown in inches and (millimeters) ordering guide model 1 tem perature range package description package option ad536ajd 0c to +70c 14- lead side - brazed ceramic dual in - line package [sbdip] d -14 AD536AJDZ 0c to +70c 14 - lead side - brazed ceramic dual in - line package [sbdip] d - 14 ad536akd 0c to +70c 14- lead sid e - brazed ceramic dual in - line package [sbdip] d -14 ad536akdz 0c to +70c 14- lead side - brazed ceramic dual in - line package [sbdip] d -14 ad536ajh 0c to +70c 10- pin metal header package [to -100] h -10 ad536ajhz 0c to +70c 10- pin metal header package [t o -100] h -10 ad536akh 0c to +70c 10- pin metal header package [to -100] h -10 ad536akhz 0c to +70c 10- pin metal header package [to -100] h -10 ad536ajq 0c to +70c 14- lead ceramic dual in - line package [cerdip] q -14 ad536akq 0c to +70c 14- lead ceramic dual in - line package [cerdip] q -14 ad536asd ?55c to +125c 14- lead side - brazed ceramic dual in - line package [sbdip] d -14 ad536asd/883b ? 55c to +125c 14- lead side - brazed ceramic dual in - line package [sbdip] d -14 ad536ase/883b ? 55c to +125c 20- termin al ceramic leadless chip carrier [lcc] e -20-1 ad536ash ? 55c to +125c 10- pin metal header package [to -100] h -10 ad536ash/883b ? 55c to +125c 10- pin metal header package [to -100] h -10 ad536aschips ? 55c to +125c die 5962 - 89805012a ? 55c to +125c 20- terminal ceramic leadless chip carrier [lcc] e -20-1 5962 - 8980501ca ? 55c to +125c 14 - lead side - brazed ceramic dual in - line package [sbdip] d - 14 5962 - 8980501ia ? 55c to +125c 10 - pin metal header package [to - 100] h - 10 1 z = rohs compliant part.
ad536a data sheet rev. e | page 16 o f 16 notes ? 1976 C 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d00504 - 0- 7/12(e)

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